NOTE: Intel® Arria® 10 FPGA (Mustang-F100-A10) Speed Grade 1 is not available since the OpenVINO 2020.3 release. If you use Intel® Vision Accelerator Design with an Intel® Arria 10 FPGA (Mustang-F100-A10) Speed Grade 1, we recommend continuing to use the Intel® Distribution of OpenVINO™ toolkit 2020.1 release.
For previous versions, see Configuration Guide for OpenVINO 2019R3, Configuration Guide for OpenVINO 2019R1, Configuration Guide for OpenVINO 2018R5.
/home/<user>/intelFPGA/18.1
directory.Download the fpga_install.sh script to the /home/<user>
directory.
a. Switch to superuser:
b. Use the fpga_install.sh
script from /home/<user>
to install your FPGA card (default is SG2).
c. To know more about the fpga_install options, invoke the script with -h
command.
d. Follow the fpga_install.sh
script prompts to finish installing your FPGA card.
e. After reboot launch the script again with same options as in step 2.b.
f. The fpga_install.sh
script creates an initialization script /home/<user>/init_openvino.sh
that should be used to setup proper environment variables.
g. To test if FPGA card was installed succesfully run aocl diagnose
:
You should see DIAGNOSTIC_PASSED
before proceeding to the next steps.
h. If you prefer to install the FPGA card manually, follow the steps 3-17 in this section and Steps to Flash the FPGA Card, otherwise you can skip to "Program a Bitstream".
Check if /etc/udev/rules.d/51-usbblaster.rules file exists and content matches with 3.b, if it does skip to next step.
a. Switch to superuser:
b. Create a file named /etc/udev/rules.d/51-usbblaster.rules and add the following lines to it (Red Hat Enterprise 5 and above):
CAUTION: Do not add extra line breaks to the .rules file.
c. Reload udev rules without reboot:
d. You can exit superuser if you wish.
NOTE: If you installed OpenVINO™ as root you will need to switch to superuser
NOTE: If you do not know which version of the board you have, please refer to the product label on the fan cover side or by the product SKU: Mustang-F100-A10E-R10 => SG2
/home/<user>/init_openvino.sh
with the following content that can be run upon opening a new terminal or rebooting. This will setup your proper environment variables. jtagconfig
to ensure that your Intel FPGA Download Cable driver is ready to use: jtagconfig
to slow the clock. The message "No parameter named JtagClock" can be safely ignored. /opt/intel/openvino/bitstreams/a10_vision_design_sg2_bitstreams/BSP/a10_1150_sg2/bringup
, where sg2_boardtest_2ddr_base.sof
is located: aocl diagnose
: DIAGNOSTIC_PASSED
.NOTE: at this point if you do not want to flash the FPGA Card you can go to "Program a Bitstream"
NOTE:
- To avoid having to reprogram the board after a power down, a bitstream will be programmed to permanent memory on the Intel® Vision Accelerator Design with Intel® Arria® 10 FPGA. This will take about 20 minutes.
- The steps can be followed below in this guide to do this.
jtagconfig
to slow the clock. The message "No parameter named JtagClock" can be safely ignored. /opt/intel/openvino/bitstreams/a10_vision_design_sg2_bitstreams/BSP/a10_1150_sg2/bringup
, where sg2_boardtest_2ddr_top.aocx
is located: sg2_boardtest_2ddr_top.aocx
file to the flash to be made permanently available even after power cycle: NOTE: You will need the USB Blaster for this.
aocl diagnose
: DIAGNOSTIC_PASSED
before proceeding to the next steps.The bitstream you program should correspond to the topology you want to deploy. In this section, you program a SqueezeNet bitstream and deploy the classification sample with a SqueezeNet model that you used the Model Optimizer to convert in the steps before.
IMPORTANT: Only use bitstreams from the installed version of the Intel® Distribution of OpenVINO™ toolkit. Bitstreams from older versions of the Intel® Distribution of OpenVINO™ toolkit are incompatible with later versions of the Intel® Distribution of OpenVINO™ toolkit. For example, you cannot use the
2019R4_PL2_FP11_AlexNet_GoogleNet_Generic
bitstream, when the Intel® Distribution of OpenVINO™ toolkit supports the2020-2_PL2_FP11_AlexNet_GoogleNet_Generic
bitstream.
Depending on how many bitstreams you selected, there are different folders for each FPGA card type which were downloaded in the Intel® Distribution of OpenVINO™ toolkit package:
/opt/intel/openvino/bitstreams/a10_vision_design_sg2_bitstreams/
. This example uses a SqueezeNet bitstream with low precision for the classification sample.NOTE: The SqueezeNet Caffe* model was already downloaded and converted to an FP16 IR when you ran the Image Classification Verification Script while installing the Intel® Distribution of OpenVINO™ toolkit for Linux* with FPGA Support. Read this section only if you want to convert the model manually, otherwise skip and go to the next section to run the Image Classification sample application.
In this section, you will create an FP16 model suitable for hardware accelerators. For more information, see the FPGA plugin section in the Inference Engine Developer Guide.
~/squeezenet1.1_FP16
: squeezenet1.1.labels
file contains the classes ImageNet
uses. This file is included so that the inference results show text instead of classification numbers. Copy squeezenet1.1.labels
to the your optimized model location: In this section you will run the Image Classification sample application, with the Caffe* Squeezenet1.1 model on your Intel® Vision Accelerator Design with an Intel® Arria® 10 FPGA.
Image Classification sample application binary file was automatically built and the FP16 model IR files are created when you ran the Image Classification Verification Script while installing the Intel® Distribution of OpenVINO™ toolkit for Windows* with FPGA Support:
~/inference_engine_samples_build/intel64/Release
directory.~/openvino_models/ir/public/squeezenet1.1/FP16/
directory.-d
option to target the FPGA: Congratulations, you are done with the Intel® Distribution of OpenVINO™ toolkit installation for FPGA. To learn more about how the Intel® Distribution of OpenVINO™ toolkit works, the Hello World tutorial and are other resources are provided below.
Use the Intel® Distribution of OpenVINO™ toolkit with FPGA Hello World Face Detection Exercise to learn more about how the software and hardware work together.
Intel® Distribution of OpenVINO™ toolkit home page: https://software.intel.com/en-us/openvino-toolkit
Intel® Distribution of OpenVINO™ toolkit documentation: https://docs.openvinotoolkit.org/
Inference Engine FPGA plugin documentation: https://docs.openvinotoolkit.org/latest/_docs_IE_DG_supported_plugins_FPGA.html