Install Intel® Distribution of OpenVINO™ toolkit for Linux with FPGA Support

NOTES:

Introduction

The Intel® Distribution of OpenVINO™ toolkit quickly deploys applications and solutions that emulate human vision. Based on Convolutional Neural Networks (CNN), the toolkit extends computer vision (CV) workloads across Intel® hardware, maximizing performance. The Intel Distribution of OpenVINO toolkit includes the Intel® Deep Learning Deployment Toolkit (Intel® DLDT).

The Intel Distribution of OpenVINO toolkit for Linux* with FPGA Support:

Included with the Installation and installed by default:

Component Description
Model Optimizer This tool imports, converts, and optimizes models that were trained in popular frameworks to a format usable by Intel tools, especially the Inference Engine. 
Popular frameworks include Caffe*, TensorFlow*, MXNet*, and ONNX*.
Inference Engine This is the engine that runs the deep learning model. It includes a set of libraries for an easy inference integration into your applications.
Drivers and runtimes for OpenCL™ version 2.1 Enables OpenCL on the GPU/CPU for Intel® processors
Intel® Media SDK Offers access to hardware accelerated video codecs and frame processing
Pre-compiled FPGA bitstream samples Pre-compiled bitstream samples for the Intel® Arria® 10 GX FPGA Development Kit, Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA, and Intel® Vision Accelerator Design with an Intel® Arria 10 FPGA.
Intel® FPGA SDK for OpenCL™ software technology The Intel® FPGA RTE for OpenCL™ provides utilities, host runtime libraries, drivers, and RTE-specific libraries and files
OpenCV version 3.4.2 OpenCV* community version compiled for Intel® hardware. Includes PVL libraries for computer vision
OpenVX* version 1.1 Intel's implementation of OpenVX* 1.1 optimized for running on Intel® hardware (CPU, GPU, IPU)
Pre-trained models A set of Intel's pre-trained models for learning and demo purposes or to develop deep learning software.
Sample Applications A set of simple console applications demonstrating how to use Intel's Deep Learning Inference Engine in your applications. Additional information about building and running the samples can be found in the Inference Engine Developer Guide.

Development and Target Platform

The development and target platforms have the same requirements, but you can select different components during the installation, based on your intended use.

Hardware

Processor Notes:

Operating Systems:

Overview

This guide provides step-by-step instructions on how to install Intel Distribution of OpenVINO toolkit with FPGA Support.  This includes FPGA initialization and configuration steps. Some steps apply only for the Intel® Arria 10 GX FPGA Development Kit and are noted as such. The following steps will be covered:

  1. Configure the Intel® Arria® 10 GX FPGA Development Kit
  2. Program the Intel® Arria® 10 GX FPGA Development Kit
  3. Install the Intel® Distribution of OpenVINO™ Toolkit and external software dependensies
  4. Configure the Model Optimizer
  5. Complete the Intel® Arria® 10 FPGA Setup
  6. Run the Demos to Verify Installation and Compile Samples
  7. Program a Bitstream
  8. Run a Sample
  9. Use the Face Detection Tutorial

NOTE: If you have the Intel® Vision Acceleration Design with Intel® Arria® 10 FPGA please start on Step 3 Install the Intel® Distribution of OpenVINO™ Toolkit.

Installation Notes:

Configure Intel® Arria® 10 GX FPGA Development Kit

NOTE: The steps in the two following sections are required only for the Intel® Arria® 10 GX FPGA Development Kit. If you have the Intel® Vision Acceleration Design with Intel® Arria® 10 FPGA, please skip to Install the Intel Distribution of OpenVINO toolkit.

To configure the Intel® Arria® 10 GX FPGA Development Kit, use the online Guide: Configuring the Intel Arria 10 GX FPGA Development Kit for OpenCL. Stop after you configure and install the Intel Arria 10 GX FPGA Development Kit board. Do not follow the steps in the rest of the document. Instead, return to this document upon completing the specified section.

initialize_STOP_copy.png

Program the Intel® Arria® 10 GX FPGA Development Kit

NOTE: You need to do this only once, after you set up the FPGA board. These steps are not necessary for the Intel® Vision Acceleration Design with Intel® Arria® 10 FPGA. If you have the Intel® Vision Acceleration Design with Intel® Arria® 10 FPGA skip to Install the Intel Distribution of OpenVINO™ toolkit.

  1. Use one of the following two links to download the Intel® Quartus® software, depending on the version you want:

    Quartus_Pro_Download.png
    Quartus_Lite_Download.png
  2. Go to the Downloads directory or the directory to which you downloaded the Intel® Quartus® package. This document assumes the software is in the Downloads directory:
    cd ~/Downloads
  3. Use the command for the package you downloaded:
    • Option 1: Intel® Quartus® Pro:
      sudo chmod +x QuartusProProgrammerSetup-17.1.0.240-linux.run
    • Option 2: Intel® Quartus® Lite:
      chmod +x QuartusProgrammerSetup-17.1.0.590-linux.run
  4. Run the Intel® Quartus® Installer:
    sudo ./Quartus.<version>.run
  5. Click through the installer to the end. Remove the checkmarks from all boxes at the end of the installation.
    By default, the software is installed under /home/user. We suggest changing this directory to /opt/altera during the installation. A subdirectory is created with the name dependent on your version of Intel® Quartus®:
    • Intel® Quartus® Pro: /opt/altera/intelFPGA_pro/17.1
    • Intel® Quartus® Lite: /opt/altera/intelFPGA/17.1
  6. Download fpga_support_files.tgz from the Intel Registration Center. The files in this .tgz are required to ensure your FPGA card and the Intel Distribution of OpenVINO work correctly.
  7. Go to the directory where you downloaded fpga_support_files.tgz.
  8. Unpack the .tgz file:
    tar -xvzf fpga_support_files.tgz
    A directory named fpga_support_files is created.
  9. Go to the fpga_support_files directory:
    cd fpga_support_files
  10. Copy setup_env.sh to your home directory:
    cp setup_env.sh /home/<user>
    source /home/<user>/setup_env.sh
  11. Configure the FPGA Driver Blacklist:
    sudo mv config/blacklist-altera-cvp.conf /etc/modprobe.d
  12. Copy the USB rules:
    sudo cp config/51-usbblaster.rules /etc/udev/rules.d/
  13. Load the USB rules:
    sudo udevadm control --reload-rules && udevadm trigger
  14. Unplug and replug the Micro-USB  cable from the Intel Arria 10 GX board for JTAG.
  15. (OPTIONAL) Validate that the cable is connected:
    lsusb | grep Altera
    You should see a message similar to:
    Bus 001 Device 005: ID 09fb:6010 Altera
  16. Run jtagconfig:
    jtagconfig
    Your output is similar to:
    USB-BlasterII [1-14]
    02E660DD 10AX115H1(.|E2|ES)/10AX115H2/..
    020A40DD 5M(1270ZF324|2210Z)/EPM2210
  17. Use jtagconfig to slow the clock:
    jtagconfig --setparam 1 JtagClock 6M
  18. (OPTIONAL) Confirm the clock is set to 6M:
    jtagconfig --getparam 1 JtagClock
    You should see the following:
    6M
  19. Go to the config directory:
    cd config
  20. Use Intel® Quartus® software to program top.sof and max5_150.pof. These files are from fpga_support_files.tgz:
    quartus_pgm -c 1 -m JTAG -o "p;max5_150.pof@2"
    quartus_pgm -c 1 -m JTAG -o "p;top.sof"
  21. Restart your computer:
    reboot
  22. Verify you successfully programmed top.sof:
    sudo lspci |grep Alt
    If successful, you see a message similar to:
    01:00.0 Processing accelerators: Altera Corporation Device 2494 (rev 01)

    NOTE: You will finish setting up the card after you install Intel Distribution of OpenVINO toolkit.

Install the Intel® Distribution of OpenVINO™ Toolkit Core Components

NOTE: An Internet connection is required to complete these steps.

If you do not have a copy of the Intel Distribution of OpenVINO toolkit package file, download it from Intel® Distribution of OpenVINO™ toolkit for Linux* with FPGA Support.

NOTE: You will need to select the Intel Distribution of OpenVINO toolkit for Linux* with FPGA Support package version from the dropdown.

  1. Open a command prompt terminal window.
  2. Go to the location where you downloaded the Intel Distribution of OpenVINO toolkit for Linux* with FPGA Support package file.
    If you downloaded the package file to the current user's Downloads directory:
    cd ~/Downloads/
    By default, the file is saved as l_openvino_toolkit_fpga_p_<version>.tgz.
  3. Unpack the .tgz file:
    tar -xvzf l_openvino_toolkit_fpga_p_<version>.tgz
    The files are unpacked to the l_openvino_toolkit_fpga_p_<version> directory.

  4. Go to the l_openvino_toolkit_fpga_p_<version> directory:

    cd l_openvino_toolkit_fpga_p_<version>

    If you have a previous version of the Intel Distribution of OpenVINO toolkit installed, rename or delete two directories:

    • /home/<user>/inference_engine_samples
    • /home/<user>/openvino_models

    Installation Notes:

    • Choose an installation option and run the related script with root or regular user privileges. The default installation directory depends on the privileges you choose for the installation.
    • You can use either a GUI installation wizard or command-line instructions. The only difference between the two options is that the command-line instructions are text-based. This means that instead of clicking options in a GUI, command-line prompts ask for input on a text screen.
    • Screenshots are provided for the GUI, but not for CLI. If you choose CLI, you will be presented with the same choices and complete the same tasks.
  5. Choose your installation option:
    • Option 1: GUI Installation Wizard:
      sudo ./install_GUI.sh
    • Option 2: Command-Line Instructions:
      sudo ./install.sh
  6. Follow the instructions on your screen. Watch for informational messages such as the following in case you must complete additional steps:
    install-linux-fpga-01.png
  7. If needed, change the components you want to install or the installation directory. Pay attention to the installation directory. You will need this information later. If you select the default options, the Installation summary GUI screen looks like this:
    install-linux-fpga-02.png
    • Optional: You can choose Customize and select only the bitstreams for your card. This will allow you to minimize the size of the download by several gigabytes.
    • The three bitstreams listed at the bottom of the customization screen are highlighted below. Choose the one for your FPGA:
      install-linux-fpga-04.png
    • If you used root privileges to run the installer, it installs the Intel Distribution of OpenVINO in the /opt/intel/computer_vision_sdk_fpga_<version>/ directory.
      For simplicity, a symbolic link to the latest installation is also created: /opt/intel/computer_vision_sdk/.
    • If you used regular user privileges to run the installer, it installs the Intel Distribution of OpenVINO in the /home/<user>/intel/computer_vision_sdk_fpga_<version>/ directory.
      For simplicity, a symbolic link to the latest installation is also created: /home/<user>/intel/computer_vision_sdk/.
  8. A Complete screen indicates the first part of installation is done. The final screen informs you that the core components have been installed and additional steps still required:
    install-linux-fpga-05.png

The first core components are installed. Continue to the next section to install additional dependencies.

Install External Software Dependencies

  1. Change to the install_dependencies directory:
    cd /opt/intel/computer_vision_sdk/install_dependencies
  2. Run a script to download and install the external software dependencies:
    sudo -E ./install_cv_sdk_dependencies.sh

These dependencies are required for:

The dependencies are installed. Continue to the next section to configure the Model Optimizer.

Configure the Model Optimizer

The Model Optimizer is a Python*-based command line tool for importing trained models from popular deep learning frameworks such as Caffe*, TensorFlow*, Apache MXNet*, and ONNX*.

The Model Optimizer is a key component of the Intel Distribution of OpenVINO toolkit. You cannot do inference on your trained model without running the model through the Model Optimizer. When you run a pre-trained model through the Model Optimizer, your output is an Intermediate Representation (IR) of the network. The Intermediate Representation is a pair of files that describe the whole model:

For more information about the Model Optimizer, refer to the Model Optimizer Developer Guide. 

Model Optimizer Configuration Steps

You can choose to either configure all supported frameworks at once, or configure one framework at a time. Choose the option that best suits your needs. If you see error messages, make sure you installed all dependencies.

NOTE: If you did not install the Intel Distribution of OpenVINO to the default install directory, replace /opt/intel/ with the directory where you installed the software. 

NOTE: Configuring the Model Optimizer requires an internet connection.

Option 1: Configure all supported frameworks at the same time

  1. Go to the Model Optimizer prerequisites directory:
    cd /opt/intel/computer_vision_sdk/deployment_tools/model_optimizer/install_prerequisites
  2. Run the script to configure the Model Optimizer for Caffe, TensorFlow, MXNet, Kaldi*, and ONNX:
    sudo ./install_prerequisites.sh

Option 2: Configure each framework separately

  1. Go to the Model Optimizer prerequisites directory:
    cd /opt/intel/computer_vision_sdk/deployment_tools/model_optimizer/install_prerequisites
  2. Run the script for your model framework. You can run more than one script:
    • For Caffe:
      sudo ./install_prerequisites_caffe.sh
    • For TensorFlow:
      sudo ./install_prerequisites_tf.sh
    • For MXNet:
      sudo ./install_prerequisites_mxnet.sh
    • For ONNX:
      sudo ./install_prerequisites_onnx.sh
    • For Kaldi:
      sudo ./install_prerequisites_kaldi.sh

The Model Optimizer is configured for one or more frameworks.

Complete Intel® Arria® 10 FPGA Setup

For the Intel Vision Accelerator Design with Intel Arria 10 FPGA, download the fpga_support_files archive:

  1. Download fpga_support_files.tgz from the Intel Registration Center. The files in this <tt>.tgz are required to ensure your FPGA card and Intel Distribution of OpenVINO toolkit work correctly. Right click or save the file instead of letting your browser extract automatically.
  2. Go to the directory where you downloaded fpga_support_files.tgz.
  3. Unpack the .tgz file:
    tar -xvzf fpga_support_files.tgz
    A directory named fpga_support_files is created.
  4. Go to the fpga_support_files directory:
    cd fpga_support_files

NOTE: These steps are for both Intel Arria 10 FPGA cards.

  1. Switch to superuser mode:
    sudo su
  2. Use the setup_env.sh script from fpga_support_files.tgz to set your environment variables:
    source /home/<user>/Downloads/fpga_support_files/setup_env.sh
  3. Change directory to /Downloads/fpga_support_files/:
    cd /home/<user>/Downloads/fpga_support_files/
  4. Run the FPGA dependencies script, which allows OpenCL to support Ubuntu and recent kernels:
    ./install_openvino_fpga_dependencies.sh 
    • When asked, select the FPGA card, Intel GPU, and Movidius Neural Compute Stick, then you can install the correct dependencies.
    • If you installed the 4.14 kernel, you will need to reboot the machine and select the new kernel in the Ubuntu (grub) boot menu. You will also need to redo steps 1 and 2 to set up your environmental variables again.
  5. Install OpenCL devices. Enter Y when prompted to install:
    aocl install
  6. Reboot the machine:
    reboot
  7. Use the setup_env.sh script from fpga_support_files.tgz to set your environment variables:
    source /home/<user>/Downloads/fpga_support_files/setup_env.sh
  8. Run aocl diagnose:
    aocl diagnose
    Your screen displays DIAGNOSTIC_PASSED.
  9. Exit superuser mode:
    exit

For the Intel Distribution of OpenVINO toolkit R5 with Intel® Vision Acceleration Design with Intel® Arria® 10 FPGA, continue to the next section to program the board before running the samples and programming bitstreams.

Otherwise, you completed the FPGA installation and configuration. You are ready to compile the samples by running the demo scripts.

Set Up the Intel® Vision Accelerator Design with Intel® Arria® 10 FPGA for R5

For the R5 release, the Intel® Distribution of OpenVINO™ toolkit introduced a new board support package (BSP) a10_1150_sg1 for the Intel® Vision Accelerator Design with an Intel® Arria 10 FPGA, which is included into the fpga_support_files.tgz archive. To program the bitstreams for the Intel Distribution of OpenVINO toolkit R5, you need to program the BSP into the board using the USB blaster:

NOTE: The steps below apply only for the Intel Distribution of OpenVINO toolkit R5. Otherwise, skip them to the Run the Demos to Verify Installation and Compile Samples.

  1. Go to the config folder of the fpga_support_files directory where the a10_1150_sg1 is located:
    cd /home/<user>/Downloads/fpga_support_files/config/
  2. Copy the a10_1150_sg1 folder to the board directory:
    sudo cp -rf a10_1150_sg1 /opt/altera/aocl-pro-rte/aclrte-linux64/board/
  3. Convert the BSP files from DOS to UNIX:
    sudo chmod +x a10_1150_sg1
    find a10_1150_sg1 -type f -print0 | xargs -0 dos2unix
  4. Set up the USB Blaster:
    1. Connect the cable between the board and the host system. Use the letter codes in the diagram below for the connection points:
      • Connect the B end of the cable to point B on the board.
      • Connect the F end of the cable to point F on the FPGA download cable.
        usb-blaster-setup.png
        Connection from JTAG Port to Cable to Intel® FPGA Download Cable
    2. From point F end of the cable to point F on the FPGA download cable, the connection is as shown:
      fpga-download-cable.png
      Connection from Cable to Intel® FPGA Download Cable
  5. Source the setup_env.sh script from the fpga_support_files to set up the environment variables:
    source /home/<user>/Downloads/fpga_support_files/setup_env.sh
  6. Update the Intel FPGA Download Cable rules to program the board without root permissions and to flash the initialization bitstreams so that the Intel FPGA Download Cable can communicate with the board: 
    sudo cp config/51-usbblaster.rules /etc/udev/rules.d
  7. Load the USB rules:
    sudo udevadm control --reload-rules && udevadm trigger
  8. Unplug and re-plug the Intel® FPGA Download Cable to enable JTAG connection.
  9. Run jtagconfig to ensure that your Intel FPFA Download Cable driver is ready to use:
    jtagconfig
    Your output is similar to:
    1) USB-Blaster [1-6]
    02E660DD 10AX115H1(.|E2|ES)/10AX115H2/..
  10. Download Quartus Prime Lite Edition 17.1. Install the Quartus Prime Lite to /home/<user>/intelFPGA/17.1 directory.

    NOTE: You will need the complete Quartus Prime Lite version when you want to program the boardtest_1ddr_top.aocx into the flash for permanent availability.

  11. Export the Quartus Prime Lite environment variable:
    export QUARTUS_ROOTDIR=/home/<user>/intelFPGA/17.1/quartus
  12. Go to /opt/altera/aocl-pro-rte/aclrte-linux64/board/a10_1150_sg1/bringup, where boardtest_1ddr_top.aocx is located:
    cd /opt/altera/aocl-pro-rte/aclrte-linux64/board/a10_1150_sg1/bringup
  13. Program the boardtest_1ddr_top.aocx file to the flash to be made permanently available even after power cycle:
    aocl flash acl0 boardtest_1ddr_top.aocx

    NOTE: You will need the USB Blaster for this.

  14. Reboot the host system.
  15. Check if the host system recognizes the Intel® Vision Accelerator Design with Intel® Arria® 10 FPGA board. Confirm you can detect the PCIe card:
    lspci | grep -i Altera
    Your output is similar to:
    01:00.0 Processing accelerators: Altera Corporation Device 2494 (rev 01)
  16. Source the setup_env.sh script from the fpga_support_files to setup the environment variables:
    source /home/<user>/Downloads/fpga_support_file/setup_env.sh
  17. Uninstall the previous R4 BSP before installing the OpenCL drivers for the R5 BSP:
    aocl uninstall /opt/altera/aocl-pro-rte/aclrte-linux64/board/<R4_BSP_package>/
  18. Export and source the environment script:
    export AOCL_BOARD_PACKAGE_ROOT=/opt/altera/aocl-pro-rte/aclrte-linux64/board/a10_1150_sg1
    source /opt/altera/aocl-pro-rte/aclrte-linux64/init_opencl.sh
  19. Install OpenCL devices:
    aocl install
  20. Run the diagnose command:
    aocl diagnose
    You should see DIAGNOSTIC_PASSED before proceeding to the next steps.

Run the Demos to Verify Installation and Compile Samples

To check the installation, run the demo applications provided with the product on the CPU using the following instructions:

  1. Go to the Inference Engine demo directory:
    cd /opt/intel/computer_vision_sdk/deployment_tools/demo

  2. Run the Image Classification demo script.
    This demo uses the Model Optimizer to convert a SqueezeNet model to the <tt>.bin and <tt>.xml Intermediate Representation (IR) files. The Inference Engine requires this model conversion so it can use the IR as input and achieve optimum performance on Intel hardware.
    This demo also builds the package sample applications.

    ./demo_squeezenet_download_convert_run.sh

    This demo uses the cars.png image in the demo directory. When the demo completes, you will have the label and confidence for the top-10 categories:

    squeezenet_results.png
  3. Run the Inference Pipeline demo script:
    ./demo_security_barrier_camera.sh
    This demo uses the car.png image in the demo directory to show an inference pipeline using three of the pre-trained models. The demo uses vehicle recognition in which vehicle attributes build on each other to narrow in on a specific attribute.
    First, an object is identified as a vehicle. This identification is used as input to the next model, which identifies specific vehicle attributes, including the license plate. Finally, the attributes identified as the license plate are used as input to the third model, which recognizes specific characters in the license plate.
    This demo also builds the sample applications included in the package.
    When the demo completes, you will see an image that displays the resulting frame with detections rendered as bounding boxes, and text:
    security-barrier-results.png
  4. Close the image viewer window to complete the demo.

To learn more about the demo applications, see the README.txt file in /opt/intel/computer_vision_sdk/deployment_tools/demo.

For a description of the Intel Distribution of OpenVINO pre-trained object detection and object recognition models provided with the package, go to /opt/intel/computer_vision_sdk/deployment_tools/intel_models/ and open index.html.

In this section, you saw a preview of the Intel Distribution of OpenVINO toolkit capabilities.

You have completed all the required installation, configuration, and build steps in this guide to use your CPU to work with your trained models.

NOTE: If you are migrating from the Intel® Computer Vision SDK 2017 R3 Beta version to the Intel Distribution of OpenVINO, read this information about porting your applications.

Program a Bitstream

The bitstream you program must correspond to the topology you want to deploy. In this section, you program a Squeezenet bitstream and deploy the classification sample with a Squeezenet model that you used the Model Optimizer to convert in the demo above.

IMPORTANT: Only use bitstreams from the installed version of the Intel Distribution of OpenVINO toolkit. Bitstreams from older versions of the Intel Distribution of OpenVINO toolkit are incompatible with later versions of the Intel Distribution of OpenVINO toolkit. For example, you cannot use the 1-0-1_A10DK_FP16_Generic bitstream, when the Intel Distribution of OpenVINO toolkit supports the 2-0-1_A10DK_FP16_Generic bitstream.

Depending on how many bitstreams you selected, there are different folders for each FPGA card type which were downloaded in the Intel Distribution of OpenVINO package:

To program a bitstream:

  1. Rerun the environment setup script:
    source /home/<user>/Downloads/fpga_support_files/setup_env.sh
  2. Go to your home directory:
    cd /home/<user>
  3. Program the bitstream using one one the following options depending on your card:
    • Program the bitstream for Intel® Arria® 10 FPGA Development Kit:
      aocl program acl0 /opt/intel/computer_vision_sdk/a10_devkit_bitstreams/2-0-1_A10DK_FP11_SqueezeNet.aocx
    • Program the bitstream for the Intel® Vision Accelerator Design with Intel® Arria® 10 FPGA:
      aocl program acl0 /opt/intel/computer_vision_sdk/bitstreams/a10_vision_design_bitstreams/4-0_PL1_FP11_SqueezeNet.aocx

Optional Steps to Flash the FPGA Card

NOTE:

  • To avoid having to reprogram the board after a power down, a bitstream will be programmed to permanent memory on the Intel® Arria® 10 GX FPGA Development Kit. This will take about 20 minutes.
  • The following steps 1-5 need to be done only once for a new Intel® Arria 10 FPGA card.
  1. Plug in the Micro USB cable to the card and your host system.
  2. Run jtagconfig to ensure that the cable is properly inserted:
    jtagconfig
  3. Use jtagconfig to slow the clock:
    jtagconfig --setparam 1 JtagClock 6M
  4. Store the Intel Arria 10 FPGA Development Kit bitstream long term on the board:
    aocl flash acl0 /opt/intel/computer_vision_sdk/a10_devkit_bitstreams/2-0-1_A10DK_FP11_SqueezeNet.aocx
  5. Store the Vision Design bistream on the board:
    aocl flash acl0 /opt/intel/computer_vision_sdk/bitstreams/a10_vision_design_bitstreams/4-0_PL1_FP11_SqueezeNet.aocx
    Your output is similar to:
    USB-BlasterII [1-14]
    02E660DD 10AX115H1(.|E2|ES)/10AX115H2/..
    020A40DD 5M(1270ZF324|2210Z)/EPM2210

Set Up a Neural Network Model for FPGA

In this section, you create an FP16 model suitable for hardware accelerators. For more information, see the FPGA plugin section in the Inference Engine Developer Guide.

  1. Create a directory for the FP16 SqueezeNet Model:
    mkdir /home/<user>/squeezenet1.1_FP16
  2. Go to /home/<user>/squeezenet1.1_FP16:
    cd /home/<user>/squeezenet1.1_FP16
  3. Use the Model Optimizer to convert an FP16 Squeezenet Caffe model into an optimized Intermediate Representation (IR):
    python3 /opt/intel/computer_vision_sdk/deployment_tools/model_optimizer/mo.py --input_model /home/<user>/openvino_models/classification/squeezenet/1.1/caffe/squeezenet1.1.caffemodel --data_type FP16 --output_dir .
  4. The squeezenet1.1.labels file contains the classes ImageNet uses. This file is included so that the inference results show text instead of classification numbers. Copy squeezenet1.1.labels to the your optimized model location:
    cp /home/<user>/openvino_models/ir/squeezenet1.1/squeezenet1.1.labels .
  5. Copy a sample image to the release directory. You will use this with your optimized model:
    sudo cp /opt/intel/computer_vision_sdk/deployment_tools/demo/car.png ~/inference_engine_samples/intel64/Release

Continue to the next section to run a sample application.

Run a Sample Application

  1. Go to the samples directory:
    cd /home/<user>/inference_engine_samples/intel64/Release

  2. Use an Inference Engine sample to run a sample application on the CPU:

    ./classification_sample -i car.png -m ~/openvino_models/ir/squeezenet1.1/squeezenet1.1.xml

    NOTE: The CPU throughput is measured in Frames Per Second (FPS). This tells you how quickly the inference is done on the hardware.

    Now run the inference using the FPGA.

  3. Add the -d option to target the FPGA:
    ./classification_sample -i car.png -m ~/squeezenet1.1_FP16/squeezenet1.1.xml -d HETERO:FPGA,CPU
    You will see the throughput on FPGA, but it may show a lower FPS. This is due to the initialization time. To account for that, the next step increases the iterations to get a better sense of the speed the FPGA can run inference at.
  4. Use the -ni option to increase the number of iterations. This option reduces the initialization impact:
    ./classification_sample -i car.png -m ~/squeezenet1.1_FP16/squeezenet1.1.xml -d HETERO:FPGA,CPU -ni 100

You have finished the Intel Distribution of OpenVINO installation for FPGA. To learn more about how OpenVINO works, refer to the Hello World tutorial and other resources provided below.

Hello World Face Detection Tutorial

Use the OpenVINO with FPGA Hello World Face Detection Exercise to learn more about how the software and hardware work together.

Additional Resources