Configuration Guide for the Intel® Distribution of OpenVINO™ Toolkit 2019R1 and the Intel® Arria® 10 FPGA GX Development Kit on Linux* (Ubuntu*/CentOS*)

NOTES:

  • For a first-time installation, use all steps.
  • Use steps 1 and 2 only after receiving a new FPGA card.
  • Repeat steps 3-6 when installing a new version of the Intel® Distribution of OpenVINO™ toolkit.
  • Use steps 4-6 when a Neural Network topology used by an Intel® Distribution of OpenVINO™ toolkit application changes.

1. Configure the Intel® Arria® 10 FPGA GX Development Kit

To configure the Intel® Arria® 10 GX FPGA Development Kit, use the instruction in the Configuring the Intel® Arria 10 FPGA GX Development Kit for the Intel® FPGA SDK for OpenCL™ guide. Stop after you configure and install the Intel® Arria® 10 FPGA GX Development Kit board. Do not follow the steps in the rest of the document. Instead, return to this document upon completing the specified section.

GX_Configure1.png

2. Program the Intel® Arria® 10 FPGA GX Development Kit

NOTE: You need to do this only once, after you set up the FPGA board.

  1. Use one of the following two links to download the Intel® Quartus® software, depending on the version you want:
  2. Go to the Downloads directory or the directory to which you downloaded the Intel® Quartus® software package. This document assumes the software is in the Downloads directory:
    cd ~/Downloads
  3. Use the command for the package you downloaded:
    • Option 1: Intel® Quartus® software Pro:
      sudo chmod +x QuartusProProgrammerSetup-18.1.0.222-linux.run
    • Option 2: Intel® Quartus® software Lite:
      chmod +x QuartusProgrammerSetup-18.1.0.625-linux.run
  4. Run the Intel® Quartus® software Installer:
    sudo ./Quartus.<version>.run
  5. Click through the installer to the end. Remove the checkmarks from all boxes at the end of the installation.
  6. By default, the software is installed under /home/user. We suggest changing this directory to /opt/altera during the installation. A subdirectory is created with the name dependent on your version of Intel® Quartus® software:
    • Intel® Quartus® software Pro: /opt/altera/intelFPGA_pro/18.1
    • Intel® Quartus® software Lite: /opt/altera/intelFPGA/18.1
  7. Download fpga_support_files.tgz from the Intel Registration Center. The files in this .tgz archive are required to ensure your FPGA card and the Intel® Distribution of OpenVINO™ toolkit work correctly.
  8. Go to the directory where you downloaded the fpga_support_files.tgz archive, by default ~/Downloads.
  9. Unpack the .tgz file:
    tar -xvzf fpga_support_files.tgz
    A directory named fpga_support_files is created.
  10. Go to the fpga_support_files directory:
    cd fpga_support_files
  11. Source setup_env.sh to set up your environment variables:
    source /home/<user>/Downloads/fpga_support_files/setup_env.sh
  12. Configure the FPGA Driver Blacklist:
    sudo mv config/blacklist-altera-cvp.conf /etc/modprobe.d
  13. Copy the USB rules:
    sudo cp config/51-usbblaster.rules /etc/udev/rules.d/
  14. Load the USB rules:
    sudo udevadm control --reload-rules &amp;&amp; udevadm trigger
  15. Unplug and replug the micro USB cable from the Intel® Arria® 10 FPGA GX board for JTAG.
  16. (OPTIONAL) Validate that the cable is connected:
    lsusb | grep Altera
    You should see a message similar to:
    Bus 001 Device 005: ID 09fb:6010 Altera
  17. Run jtagconfig:
    jtagconfig
    Your output is similar to:
    USB-BlasterII [1-14]
    02E660DD 10AX115H1(.|E2|ES)/10AX115H2/..
    020A40DD 5M(1270ZF324|2210Z)/EPM2210
  18. Use jtagconfig to slow the clock:
    jtagconfig --setparam 1 JtagClock 6M
  19. (OPTIONAL) Confirm the clock is set to 6M:
    jtagconfig --getparam 1 JtagClock
    You should see the following:
    6M
  20. Go to the config directory:
    cd config
  21. Use Intel® Quartus® software to program top.sof and max5_150.pof. These files are from the fpga_support_files.tgz archive:
    quartus_pgm -c 1 -m JTAG -o "p;max5_150.pof@2"
    quartus_pgm -c 1 -m JTAG -o "p;top.sof"
  22. Restart your computer:
    reboot
  23. Verify that you successfully programmed top.sof:
    sudo lspci |grep Alt
    If successful, you see a response similar to:
    01:00.0 Processing accelerators: Altera Corporation Device 2494 (rev 01)

3. Complete Intel® Arria® 10 FPGA Setup

  1. Download fpga_support_files.tgz from the Intel Registration Center. The files in this .tgz are required to ensure your FPGA card and Intel® Distribution of OpenVINO™ toolkit work correctly. Right click or save the file instead of letting your browser extract automatically.
  2. Go to the directory where you downloaded fpga_support_files.tgz, by default ~/Downloads.
  3. Unpack the .tgz file:
    tar -xvzf fpga_support_files.tgz
    A directory named fpga_support_files is created.
  4. Go to the fpga_support_files directory:
    cd fpga_support_files
  5. Switch to superuser:
    sudo su
  6. Use the setup_env.sh script from fpga_support_files.tgz to set your environment variables:
    source /home/<user>/Downloads/fpga_support_files/setup_env.sh
  7. Change directory to Downloads/fpga_support_files/:
    cd /home/<user>/Downloads/fpga_support_files/
  8. Run the FPGA dependencies script, which allows OpenCL™ to support Ubuntu* and recent kernels:
    ./install_openvino_fpga_dependencies.sh
  9. When asked, select the FPGA card, Intel® GPU, and Intel® Movidius™ Neural Compute Stick, then you can install the correct dependencies.
  10. If you installed the 4.14 kernel, you will need to reboot the machine and select the new kernel in the Ubuntu (grub) boot menu. You will also need to redo steps 1 and 2 to set up your environmental variables again.
  11. Install OpenCL™ devices. Enter Y when prompted to install:
    aocl install
  12. Reboot the machine:
    reboot
  13. Use the setup_env.sh script from fpga_support_files.tgz to set your environment variables:
    source /home/<user>/Downloads/fpga_support_files/setup_env.sh
  14. Run aocl diagnose:
    aocl diagnose
    Your screen displays
    DIAGNOSTIC_PASSED

4. Program a Bitstream

The bitstream you program should correspond to the topology you want to deploy. In this section, you program a SqueezeNet bitstream and deploy the classification sample with a SqueezeNet model that you used the Model Optimizer to convert in the example above.

IMPORTANT: Only use bitstreams from the installed version of the Intel® Distribution of OpenVINO™ toolkit. Bitstreams from older versions of the Intel® Distribution of OpenVINO™ toolkit are incompatible with later versions. For example, you cannot use the 1-0-1_A10DK_FP16_Generic bitstream, when the Intel® Distribution of OpenVINO™ toolkit supports the 2-0-1_A10DK_FP16_Generic bitstream.

There are different folders for each FPGA card type which were downloaded in the Intel® Distribution of OpenVINO™ toolkit package. For the Intel® Arria 10 FPGA GX Developer Kit, the pre-trained bitstreams are in the /opt/intel/computer_vision_sdk/bitstreams/a10_devkit_bitstreams directory. This example uses a SqueezeNet bitstream with low precision for the classification sample.

  1. Rerun the environment setup script:
    source /home/<user>/Downloads/fpga_support_files/setup_env.sh
  2. Change to your home directory:
    cd /home/<user>
  3. Program the bitstream for Intel® Arria® 10 FPGA GX Development Kit:
    aocl program acl0 /opt/intel/computer_vision_sdk/a10_devkit_bitstreams/2019R1_A10DK_FP11_SqueezeNet.aocx

Optional Steps to Flash the FPGA Card

NOTE:

  • To avoid having to reprogram the board after a power down, a bitstream will be programmed to permanent memory on the Intel® Arria® 10 FPGA GX Development Kit. This will take about 20 minutes.
  • The following steps 1-5 need to be done only once for a new Intel® Arria® 10 FPGA card.
  1. Plug in the micro USB cable to the card and your host system.
  2. Run jtagconfig to ensure that the cable is properly inserted:
    jtagconfig
  3. Use jtagconfig to slow the clock:
    jtagconfig --setparam 1 JtagClock 6M
  4. Store the Intel® Arria® 10 FPGA GX Development Kit bitstream long term on the board:
    aocl flash acl0 /opt/intel/computer_vision_sdk/a10_devkit_bitstreams/2019R1_A10DK_FP11_SqueezeNet.aocx
    Your output is similar to:
    USB-BlasterII [1-14]
    02E660DD 10AX115H1(.|E2|ES)/10AX115H2/..
    020A40DD 5M(1270ZF324|2210Z)/EPM2210

5. Setup a Neural Network Model for FPGA

In this section, you create an FP16 model suitable for hardware accelerators. For more information, see the FPGA plugin section in the Inference Engine Developer Guide.

  1. Create a directory for the FP16 SqueezeNet Model:
    mkdir /home/<user>/squeezenet1.1_FP16
  2. Go to /home/<user>/squeezenet1.1_FP16:
    cd /home/<user>/squeezenet1.1_FP16
  3. Use the Model Optimizer to convert an FP16 SqueezeNet Caffe* model into an optimized Intermediate Representation (IR):
    python3 /opt/intel/computer_vision_sdk/deployment_tools/model_optimizer/mo.py --input_model /home/<user>/openvino_models/FP32/classification/squeezenet/1.1/caffe/squeezenet1.1.caffemodel --data_type FP16 --output_dir .
  4. The squeezenet1.1.labels file contains the classes ImageNet uses. This file is included so that the inference results show text instead of classification numbers. Copy squeezenet1.1.labels to the your optimized model location:
    cp /home/<user>/openvino_models/ir/squeezenet1.1/FP32/squeezenet1.1.labels .
  5. Copy a sample image to the release directory. You will use this with your optimized model:
    sudo cp /opt/intel/computer_vision_sdk/deployment_tools/demo/car.png ~/inference_engine_samples/intel64/Release

6. Run a Sample Application

  1. Go to the samples directory
    cd /home/<user>/inference_engine_samples/intel64/Release
  2. Use an Inference Engine sample to run a sample application on the CPU:
    ./classification_sample -i car.png -m ~/openvino_models/ir/squeezenet1.1/FP32/squeezenet1.1.xml
    Note the CPU throughput in Frames Per Second (FPS). This tells you how quickly the inference is done on the hardware. Now run the inference using the FPGA.
  3. Add the -d option to target the FPGA:
    ./classification_sample -i car.png -m ~/squeezenet1.1_FP16/squeezenet1.1.xml -d HETERO:FPGA,CPU
    The throughput on FPGA is listed and may show a lower FPS. This is due to the initialization time. To account for that, the next step increases the iterations to get a better sense of the speed the FPGA can run inference at.
  4. Use -ni to increase the number of iterations, this option reduces the initialization impact:
    ./classification_sample -i car.png -m ~/squeezenet1.1_FP16/squeezenet1.1.xml -d HETERO:FPGA,CPU -ni 100

Congratulations, You are done with the OpenVINO installation for FPGA. To learn more about how the Intel® Distribution of OpenVINO™ toolkit works, the Hello World tutorial and are other resources are provided below.

Hello World Face Detection Tutorial

Use the Intel® Distribution of OpenVINO™ toolkit with FPGA Hello World Face Detection Exercise to learn more about how the software and hardware work together.

Additional Resources

Intel® Distribution of OpenVINO™ toolkit home page: https://software.intel.com/en-us/openvino-toolkit

Intel® Distribution of OpenVINO™ toolkit documentation: https://docs.openvinotoolkit.org/

Inference Engine FPGA plugin documentation: https://docs.openvinotoolkit.org/latest/_docs_IE_DG_supported_plugins_FPGA.html